Flip-Chip packaging technology is widely used for packaging in the mobile application space. Different first-level interconnect principles, the connection between the chip and the Flip Chip Substrate, were developed to address the needs of, for example, smaller pitch, of future technology nodes. The first level interconnects also serve as mechanical joints between the die and substrate and thus couple chip mechanically to the substrate. During reliability testing a large deformation, caused by the mismatch in thermal expansion is observed. This is known to lead to defects (cracks) in the brittle low-k-layers of the chip.
For 40 nm front end technology and following generations a polymer dielectric layer on the die was introduced. This layer acts as a stress buffer and protects the ultra-low-k-layers from mechanical damage. During the package process and especially after the assembly on a printed circuit board (PCB), in addition to the residual stresses and the ultra-low-k stack thermal mismatch stresses of the wafer processes, the global thermal mismatch of the package internally and between package and board causes stress on the copper/low-k- and ultra-low-k-structures.
For future technology nodes beyond today's available technologies the introduction of (porous) low-k-layers will be needed to allow higher speed and higher density. These (porous) low-k-layers with k<2.5 can be reached by introducing air gaps (air k=1). The air gaps will lead to a very brittle layer, which will be very sensitive to mechanical forces. Probably the application of a dielectric on the active chip surface will not be sufficient to prevent the (porous) low-k-layer from cracking due to the stress which is transferred from especially the first-level interconnects (solder bumps or copper columns)